Circuit design techniques for on-chip power supply noise monitoring system

Abstract

This paper describes the novel design of an on-chip noise-monitoring device, which can measure the power supply noise of each individual macro and determine the noise interference between different macros. A hierarchical noise-monitoring system is proposed to monitor and store the power supply noise information for core-based design, as part of the built-in-self-test system. The method can be further extended from system-on-chip to system-on-package to provide a complete coverage of noise testing methodology. The circuit of a properly-sized noise monitor has been simulated with the actual VDD and GND noise waveforms of a 4-GHz benchmark microprocessor to verify its functionality. © Springer-Verlag Berlin Heidelberg 2005.