Novel design method and design flow of block cipher co-processor is presented based on the WDDL (Wave Dynamic Differential Logic) and Wave-Pipelining techniques. This design flow utilized the current commercially available EDA (Electronic Design Automatic) tools to a large degree. The WDDL and wave-pipelining based coprocessor not only resists power analysis, but also achieves high performance and low power consumption in nature. According to the design flow, this paper implements a DES coprocessor. The simulation results show that the novel design method does achieve high performance, low power consumption and power analysis resistant ability at the cost of chip area. © Springer-Verlag Berlin Heidelberg 2006.
CITATION STYLE
Yuanman, T., Zhiying, W., Kui, D., & Hongyi, L. (2006). Designing power analysis resistant and high performance block cipher coprocessor using WDDL and wave-pipelining. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4318 LNCS, pp. 66–77). https://doi.org/10.1007/11937807_6
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