In this work we present different hardware implementations of a multi-layer perceptron for speech recognition. The designs have been defined using two different abstraction levels: register transfer level (VHDL) and a higher algorithmic-like level (Handel-C). The implementations have been developed and tested into a reconfigurable hardware (FPGA) for embedded systems. A study of the two considered approaches costs (silicon area), speed and required computational resources is presented. © Springer-Verlag Berlin Heidelberg 2003.
CITATION STYLE
Ortigosa, E. M., Ortigosa, P. M., Cañas, A., Ros, E., Agís, R., & Ortega, J. (2003). FPGA implementation of multi-layer perceptrons for speech recognition. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2778, 1048–1052. https://doi.org/10.1007/978-3-540-45234-8_117
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