Efficient VLSI layout of WK-recursive and WK-pyramid interconnection networks

Abstract

The WK-recursive mesh and WK-pyramid networks are recursively-defined hierarchical interconnection networks with excellent properties which well idealize them as alternatives for mesh and traditional pyramid interconnection topologies. They have received much attention due to their favorable attributes such as small diameter, large connectivity, and high degree of scalability and expandability. In this paper, we deal with packagibility and layout area of these networks. These properties are of great importance in the implementation of interconnection networks on chips. We show that WK-recursive, mesh-pyramid and WK-pyramid networks can be laid out in an area of O(N2) which is the optimal area for VLSI layout of networks. Also, we obtained the number of tracks for laying nodes in a collinear model, where the chips are multi-layered. © 2008 Springer-Verlag.