Analog VLSI Implementation of Neural Network Architecture for Signal Processing

Abstract

Biological systems process the analog signals like image and sound efficiently. To process the information the way biological systems do, we make use of Artificial Neural Networks(ANN). The focus of this paper is the implementation of the Neural Network Architecture(NNA) with on chip learning in analog VLSI for generic signal processing applications. The artificial neural network architecture comprises of analog components like multipliers and addders along with the tan-sigmoid function circuit. The proposed neural architecture is trained using Back Propagation (BP) algorithm in the analog domain. New techniaues for weight storage with refresh is proposed. The neural architecture is thus a complete analog structure. The multiplier block is implemented using gilbert cell, the tansig function is realized using MOS transistor. The functionality of the designed neural architecture is verified for analog operation like amplification and frequency multiplication. The netowk designed is adopted for image compression in analog domain. The output level swings achieved for the designed neural architecture are ±2.8 Vpp max for ± 3 V voltage supply. The circuit converged for 10 MHz signal within 200 ns. Neural architecture is also verified for Digital operations like AND, OR, NOT and XOR. The network realizes its functionality for the trained targets, which is verified using simulation results. The network designed is extended for image compression in analog domain. 50% image compression is achieved using the proposed neural network architecture. Layout design and verification of the proposed design is carried out using cadence virtuoso and synopsys hspice. The chip dimensions are 150μm2. © EuroJournals Publishing, Inc. 2009.