Low power and storage efficient parallel lookup engine architecture for IP packets

Abstract

Ternary Content-Addressable Memories are becoming very popular for designing high-throughput address lookup engines on routers: they are fast, cost-effective and simple to manage. Despite the TCAMs speed, their high power consumption is their major drawback.In this document, we designed a heuristic to match entries in TCAM stages so that only a bounded number of entries are looked up during the search operation. The performance evaluation of the proposed approach shows that it can save considerable amount of routing table's power consumption. © 2008 Springer-Verlag.