Designing and implementing FPGA for AES

Abstract

The execution of DES and triple DES is not possible on hardware platform because they consume huge memory space. We can use field programmable gate arrays in order to do the hardware implementation because of its low charge, advertising space and reconfiguration nature. This paper aims at reducing the delay by using pipeline for speeding up the process. The proposed pipeline structure has a characteristic of having round keys which during iterations of encryption are utilized and an encryption method is used for generating them in parallel. The overall delay related to a delay of coding of plaintext block is reduced. The simulation is done in VHDL by Xilinx and implementation is done on FPGA Spartan 3E.