Study and analysis of subthreshold leakage current in sub-65 nm NMOSFET

Abstract

As the technology scales down, the subthreshold leakage increases exponentially which leads to a dramatic increase in static power consumption especially in nanoscale devices. Consequently, it is very important to understand and estimate this leakage current so that various leakage minimization techniques can be devised. So in this paper we attempt to estimate the subthreshold leakage current in an NMOSFET at 16, 22, 32 and 45 nm technology nodes. Various factors which affect the subthreshold leakage such as temperature, drain induced barrier lowering (DIBL) and other short channel effects have also been explored. All the measurements are carried out using extensive simulation on HSPICE circuit simulator at various technology nodes.