Programming reconfigurable decoupled application control accelerator for mobile systems

Abstract

This paper presents an innovative multimedia reconfigurable accelerator for mobile systems associated to a programming model and a compiler flow. The architecture implements a flexible memory subsystem based on software controlled scratchpad shared memory banks. The main concern of the paper is shared memory management as it is a dominant factor in current designs and influences the performance of embedded systems as well as their energy consumption. An embedded shared-memory programming model is presented that abstracts the details of the hardware architecture but yet exposing parallelism to the user. It is open and user friendly while the hardware can execute complex data feeding on heavily pipelined datapath for compute intensive kernels. The architecture has been designed, and synthesized for 65nm technology for an operating frequency of 200MHz. © 2008 Springer-Verlag Berlin Heidelberg.