Morphable multipliers

Abstract

The design of MFUs relies on the identification, selection, and sharing of adder chains. The identification phase uses timing slacks to identify re-usable adder cells. In a 16 × 16-bit tree multiplier, the percentage of reusable adder cells in the PPRT ranges from 45% with no speed penalty to 100% for a 30% speed penalty. The selection phase extracts a maximum cover of adder chains that are present in both modes of the MFU. The implementation phase adds multiplexers at the inputs of the required adder cells. Using these techniques, five different morphable multiplier designs were evaluated. The reduction in transistors, when all MFUs run at the maximum speed, is between 8.9% and 21.5%. We evaluated the performance impact of MFUs in the context of an embedded processor. Nine kernels were scheduled on two platforms that were identical except that one had MFUs and one did not. The schedule for the kernels on the platform with MFUs was up to 43.3% faster than the platform without MFUs. © Springer-Verlag Berlin Heidelberg 2002.