Improved way prediction policy for low-energy instruction caches

Abstract

In this paper, a multi-way way prediction policy (MWWP) with a two-port Way Predictor (TPWP) is proposed for reducing the dynamic and leakage energy in multi-way set associative drowsy I-Cache without dramatic loss of performance. One port of TPWP is used for predicting the matching way in current set, only the predicted way and not all the ways is accessed to reduce the dynamic energy. The other is used for predicting the matching way in subsequent set, only the cache line in predicted way is pre-woken up from the drowsy mode to reduce the leakage energy. Different with the traditional way prediction policy, the MWWP has the lower performance overhead by selecting multiple ways speculatively for each access to improve way prediction hit ratio (WPHR). The simulation and estimation results show that, in a 4-way set-associative drowsy I-Cache, with 0.98% and 0.4% performance overhead respectively, our proposed 2-way and 3-way way prediction policy with TPWP can reduce 59% and 47% of energy in I-Cache, and save the 6.1% and 5.4% of the whole processor energy. The EDP is improved by 4.5% and 4.1% on average. © Springer-Verlag Berlin Heidelberg 2007.