On steiner minimal trees in grid graphs and its application to VLSI routing

Abstract

In this paper we present an algorithm for Steiner minimal trees in grid graphs with all terminals located on the boundary of the graph. The algorithm runs in O(k2 * min{k2 log k, n}) time, where k and n are the numbers of terminals and vertices of the graph, respectively. It can handle non-convex boundaries and is the fastest known for this case. We also describe a new approach to the homotopic routing problem in VLSI layout design, which applies our Steiner tree algorithm to construct minimum-length wires for multi-terminal nets.