A novel adder cell for ultra low voltage, ultra low power networks in nanoscale VLSI circuits

Abstract

A novel full adder cell is designed so that it can overcome the challenges of circuit design in deep submicron (DSM) technology. The proposed adder cell utilizes multiplexing control input techniques (MCIT) for the sum operation and uses a new arrangement of pass transistors for carry operation. The adder is then used in an 8×8bit Braun-array multiplier to show its performance. The layout of multi- plier is simulated in 32nm CMOS technology by Microwind31 (MW31) VLSI CAD TOOL. Simulated results show that our circuit operates properly in nanoscale and has a very small area. © IEICE 2011.