To adress the problem of static power consumption, approaches as ABB and AVS have been proposed to reduce runtime leakage in integrated circuits. Applying these techniques is a trade off between power and delay, which is best decided early in the design flow. Therefore high level power and delay estimation is needed. In our work, we present a fast RT Level delay macro model considering supply and bias voltages and temperature. Errors below 5% combined with only few characterization data enables this approach to be used by high level design tools to support leakage optimization by e.g. ABB and AVS. © Springer-Verlag Berlin Heidelberg 2007.
CITATION STYLE
Hoyer, M., Helms, D., & Nebel, W. (2007). Modelling the impact of high level leakage optimization techniques on the delay of RT-components. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4644 LNCS, pp. 171–180). Springer Verlag. https://doi.org/10.1007/978-3-540-74442-9_17
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