Effect of Metallic Strip Deposition Within the Source Dielectric with Applied Double Metallic Drain for Enhanced DC/RF Behavior of Charge Plasma TFET for Low-Power IOT Applications

Abstract

Wide tunneling barrier is always a hurdle to achieve acceptable electrical behavior for charge plasma TFET. Poor tunneling rate of charge carriers results in the degraded switching speed of the charge plasma TFET for low-power analog applications. In this concern, deposition of a thin metallic strip within the dielectric at channel/source junction enhances the DC characteristics like threshold voltage, subthreshold swing, and ON current of the device. Simultaneously, double metallic drain technique employed at drain side reduces ambipolar (negative conduction) nature of device. This article consists of a comparative analysis of conventional charge plasma TFET with modified structure. Inverter implementation of conventional and modified structures is also performed for the adaptability of devices for low-power IoT applications.