FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures

Abstract

The main objective is to detect and reduce the faults in full adder design using self checking and self repairing adder block. The rate of chip failure is directly proportional to chip density. This fault tolerant adder has high speed (Delay is 6.236ns) & implemented on FPGA Spartan 3 using XC3S50 device. The source code is written in verilog. In this design faults are identified and repaired using self checking and self repairing full adder methodologies