Classification and performance of reconfigurable architectures

Abstract

Recently, several systems have been designed which use reconfigurable logic to perform general purpose computation. While the number of these systems being constructed continues to increase, their relationship to conventional architectures is not clear. This paper proposes a model which unifies traditional instruction set architectures with reconfigurable architectures. From this model, four major architectural categories of reconfigurable machines are given. From this classification, issues of performance, programmability and scalability are addressed.