Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution

Abstract

The paper presents a technique called Global Instruction Distribution that globally fine-tunes the code produced for a superscalar processor. The fine-tuning is effected by disbributing instructions from one block to other blocks according to the control flow graph of the program. The method does not involve instruction scheduling, but models resource usage to find the best insertion points in the target basic block. We present our implementation of GID in a production compiler, and show how the GID framework allows incorporation of additional functions targeting different optimizations. Performance measurements on the MIPS R8000 are presented to demonstrate the practicality and efficacy of this approach.