Design tools and methods for chip physical design

Abstract

This chapter presents a new approach for the physical design of integrated systems, as the MPSoCs, where all logic cells are designed on the fly, without the limitations that a physical designer faces when using a cell library (number of functions, number of transistors, transistor sizing, area, and power consumption). Many functional blocks compose MPSoCs and several of them are composed by random logic. So, it is important to optimize these random logic blocks by using only the needed transistors and using the right sizing. Then there is demand of EDA to cope with this goal. A basic tool to minimize the number of transistors is the one that provides degeneration of any logical function using the optimal number of transistors. A cell generator allows the automatic design of cells composed by any transistor network (using simple gates or static CMOS complex gates - SCCG) and having any transistor sizing. When the size of the transistor should be bigger than the cell height, the tool is able to do transistor folding. As the designer is free from the limitations of a cell library, it is possible to do a deep logic minimization where all needed logic cells will be generated on the fly. This allows a reduction in the number of needed transistors to implement a circuit. As a consequence, the static power consumption will also be reduced. The cell generator provides cells with a compacted layout, allowing a significant transistor density. It is presented some physical design automation strategies related to transistor topologies, management of routing in all layers, VCC and Ground distribution, clock distribution, contacts and vias management, body ties management, transistor sizing and folding, and the how these strategies can improve the layout optimization. Some results are compared with the ones obtained with traditional standard cells tools (vendor's tools), showing the gain in area, delay, and power consumption. The flexibility of the approach can also let the designers to define the layout parameters to cope with problems such as tolerance to transient effects, yield improvement, printability, etc. The designer can also manage the sizing of transistors to reduce power consumption, without compromising the clock frequency. © 2011 Springer Science+Business Media, LLC.