A single chip HDTV encoder LSI for H.264/AVC high422P@L4.1

Abstract

We have developed a single-chip HDTV encoder LSI for H.264/AVC High422P@L4.1 that is optimized for broadcasting transport systems. Significant bit-rate reduction around 50% or more relative to MPEG-2 can be achieved by originally developed motion vector coding algorithm and subjective quality enhancement through adaptive bit allocation considering human visual system. It also enables low-delay encoder implementation with at shortest 50ms encoding delay, with advanced coding control that optimizes the balance of buffering delay and coded image quality as well as variable delay time control mechanism. We adopt a hierarchical multi-CPU framework and CPU interface those enable flexible encoder control per GOP/Picture/MB, to realize various image quality and encoding delay adjustments. This LSI is fabricated in a 90-nm CMOS process and can be integrated in a 9×9 mm2 chip.