This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13μm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18μm CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages. © Springer-Verlag Berlin Heidelberg 2004.
CITATION STYLE
Wilton, S. J. E., Ang, S. S., & Luk, W. (2004). The impact of pipelining on energy per operation in field-programmable gate arrays. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 3203, 719–728. https://doi.org/10.1007/978-3-540-30117-2_73
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