We present an analog-VLSI neural network for image recognition which features a dimensionality reduction network and a classification stage. We implement local learning rules to train the network on chip or program the coefficients from a computer, while compensating for the negative effects of device mismatch and circuit nonlinearity. Our experimental results show that the circuits perform closely to equivalent software implementations, reaching 87% accuracy for face classification and 89% for handwritten digit classification. The circuit dissipates 20mW and occupies 2.5mm 2 of die area in a 0.35μm CMOS process. © 2009 Springer Berlin Heidelberg.
CITATION STYLE
Carvajal, G., Valenzuela, W., & Figueroa, M. (2009). Image recognition in analog VLSI with on-chip learning. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 5768 LNCS, pp. 429–438). https://doi.org/10.1007/978-3-642-04274-4_45
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