Abstract
In this paper we present an approach for handoptimized pipelined FPGA-multipliers, namely carry save array multipliers (CSM). By a detailed adaptation to the underlying architecture of XC4013E-3 FPGAs, we derive high throughput and compact implementation of FPGA-Multipliers. By means of a sophisticated pipelining scheme, clock frequencies of up to 96MHz are achievable for operand’s wordthwidth of up to 10 bits.
Cite
CITATION STYLE
Do, T. T., Kropp, H., Schwiegershausen, M., & Pirsch, P. (1997). Implementation of pipelined multipliers on Xilinx FPGAs. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1304, pp. 51–60). Springer Verlag. https://doi.org/10.1007/3-540-63465-7_210
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