Null convention logic circuits using balanced ternary on SOI

Abstract

We propose and analyze novel Ternary logic circuits targeting an asynchronous Null Convention Logic (NCL) pipeline where the Null value (i.e. Data not valid) is used to make the pipeline self-synchronizing and delay insensitive. A balanced Ternary logic system is used, in which the logic set {High Data, Null, Low Data} maps to voltage levels {+V DD, 0V, -V DD}. Low power circuits such as Ternary to Binary converter, DATA/NULL Detector and Ternary Register are described based a 45nm SOI process technology that offers multiple simultaneous transistor thresholds. © 2012 Springer-Verlag GmbH.