A combined approach to high-level synthesis for dynamically reconfigurable systems

Abstract

In this paper, two complementary design models and related synthesis techniques are combined to capture behavioral and structural information in modelling and synthesizing a dynamically reconfigurable system. The proposed formulation is achieved by using finite domain constraints and related constraint-solving techniques offered by constraint logic programming. Our formulation represents operation-level temporal constraints and dynamic resource constraints in a unified model. Different synthesis tasks, such as temporal partitioning, scheduling and dynamic module allocation can be modelled in this framework, enabling the discovery of an optimal or near optimal solutions. Experiments have been carried out using a prototype of the high-level synthesis system implemented in CHIP, a constraint logic programming system. Current experimental results show that our approach can provide promising synthesis results in terms of the synthesis time and the number of reconfigurations.