Future trends in electronic packaging

Abstract

Electronic packaging is traditionally defined as the back-end process that transforms bare integrated circuits (IQ into functional products. As the IC feature size decreases and the size of silicon wafer increases, the cost per IC is reduced and the performance is enhanced. The future IC chips will be larger in size, have more input/output terminals (I/Os), and require higher power. In addition to the advancements in IC technology, electronic packaging is also driven by the market requirements for low cost, small size, and multi-functional electronic products. In response to these requirements, packaging related areas such as design, packaging architectures, materials, processes, and manufacturing equipment are all changing rapidly. Wafer-level packaging (WLP) offers the benefits of low cost and smallest size for single chip packages, since the package is done at wafer level other than individual die. After packages reach the horizontal limit of dimensions, 3D stacking solution provides more efficient packages through expanding packages in the vertical dimension. Functional integration is achieved with 3D stacking architectures. System in package (SIP), one of the solutions to system integration, incorporates electronics, non-electronic devices such as optical devices, biological devices, micro-electro-mechanical systems (MEMS), etc, and interconnection in a single package, to form smart structures or microsystems. MEMS devices require specialized packaging to serve new market applications. This paper and presentation describe the technology requirements and challenges of these advancing packaging areas. The potential solutions and future trends are presented.