Impact of Temperature on Circuit Metrics of Various Full Adders

Abstract

This research work emphasizes the effect of temperature variation on circuit metrics of distinct 1-bit full adder circuits operating at low voltage. This work is studied using 90 nm MOSFET technology. The design styles employed for constructing the adders are conventional complementary metal-oxide semiconductor (CMOS), complementary pass-transistor logic (CPTL) and transmission gate (TG). Cadence Virtuoso is used for designing and simulation of the circuits. The circuit metrics such as average power, delay and power delay product (PDP) are calculated from the simulation results. On comparison of the results, it is evident that average power and PDP of CPTL adder remain least affected by temperature, while the delay of CMOS adder remains least affected by temperature.