Efficient hardware architectures for AES on FPGA

Abstract

This paper presents design, implementation and comparison of highly efficient architectures for AES on FPGAS: Iterative architecture and pipelined architecture. The first design is optimized for area and the second one is optimized for speed. Implementation of AES algorithm involves design of two key functional operations namely Substitute Byte/InvSubstitute Byte and MixColumn/InvMixColumn in each round unit for encryption/decryption leading to area and speed bottlenecks.The suggested architectures exploit functional block resource sharing between encryption, decryption as well as on-the-fly key generation. Both designs use dedicated BRAM's for SubstituteByte/ InvSubstituteByte functional blocks and combinational logic for MixColumn/InvMixColumn functions based on byte level decomposition. The two designs have been implemented on Xilinx Virtex II -XC2VP30 device. The Iterative architecture consumes 945 slices and 3 BRAM's and is more compact compared to the designs reported. The proposed pipelined architecture for improved throughput uses a total resource of 12556 slices and 100 BRAMs with a throughput of 47.7 Gbps , the fastest design reported so far. These designs cater to different applications from high performance e-commerce IPsec servers to low power mobile and home applications. © 2011 Springer-Verlag.