The presented Triple-DES encryptor is a single-chip solution to encrypt network communication. It is optimized for throughput and fast switching between virtual connections like found in ATM networks. A broad range of optimization techniques were applied to reach encryption rates above 155 Mbps even for Triple-DES encryption in outer CBC mode. A high-speed logic style and full-custom design methodology made first-time working silicon on a standard 0.6 μm CMOS process possible. Correct functionality of the prototype was verified up to a clock rate of 275 MHz. © Springer-Verlag Berlin Heidelberg 2000.
CITATION STYLE
Leitold, H., Mayerwieser, W., Payer, U., Posch, K. C., Posch, R., & Wolkerstorfer, J. (2000). A 155 Mbps Triple-DES network encryptor. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1965 LNCS, pp. 164–174). Springer Verlag. https://doi.org/10.1007/3-540-44499-8_12
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