Evaluation Platform of Time-Domain Computing-in-Memory Circuits

Abstract

Computing-in-memory (CIM) architecture is considered an effective way to reduce the energy efficiency of deep neural networks (DNNs). Compared with conventional all digital implementations, time-domain CIM designs have shown great potential with better energy efficiency and less area cost. However, due to the non-idealities of devices and PVT variations, time-domain CIM may face computational errors, resulting in the reduction of network accuracy. In this brief, we proposed an evaluation platform based on typical time-domain CIM circuits to optimize the design process. Non-idealities in CIM calculation and the impact of key parameters on the network accuracy were analyzed. Based on this evaluation platform, a 28nm time-domain CIM test chip with configurable computing channels was fabricated. Under 2-128 computing channels, the measurement results show the same trend as proposed evaluation platform. And this chip achieved 66.8 TOPS/W energy efficiency and 80.68% inference accuracy based on the CIFAR-10 dataset.