A (fault-tolerant)2 scheduler for real-time HW tasks

Abstract

This paper describes a fault-tolerant scheduler that uses the Area-Time response Balancing algorithm (ATB) for scheduling real-time hardware tasks onto partially reconfigurable FPGAs. The architecture of the ATB scheduler incorporates fault-tolerance by design features; including Triple Modular Redundancy (TMR), parity protection of its memories and finite state machines, as well as spatial and implementation diversity. Additionally, it is able to scrub soft-errors and circumvent the permanent damage in the device. Besides the scheduling circuit is itself fault-tolerant, ATB is aware of the occurring faults in the silicon substrate of the chip, leading to a very reliable "fault-tolerant square scheduling". © 2011 Springer-Verlag.