Performance characterization of the 64-bit×86 architecture from compiler optimizations' perspective

Abstract

Intel Extended Memory 64 Technology (EM64T) and AMD 64-bit architecture (AMD64) are emerging 64-bit x86 architectures thai are fully x86 compatible. Compared with the 32-bit x86 architecture, the 64-bit x86 architectures cater some new features to applications. For instance, applications can address 64 bils of virtual memory space, perform operations on 64-bil-wide operands, gel access to 16 general-purpose registers (GPRs) and 16 extended multi-media (XMM) registers, and use a register-based argument passing convention, In this paper, we investigate the performance impacts of these new features from compiler optimizations' standpoint. Our research compiler is based on the Intel Fortrnn/C++ production compiler, and our experiments arc conducted on the SPRC2000 benchmark suite, Results show that for 64-bit-wide pointer and long data types, several SPEC2000 C benchmarks are slowed down by more than 20%, which is mainly due to the enlarged memory footprint. To evaluate the performance poiential of 64-bit x86 architectures, we designed and implemented the LP32 code model such that the sizes of pointer and long are 32 bits. Our experiments demonstrate that on average the LP32 code model speeds up the SPEC2000 C benchmarks by 13.4%. For the register-based argument passing convention, our experiments show that the performance gain is less than 1% because of the aggressive function inlining optimization Finally, we observe that using 16 GPRs and 16 XMM registers significantly outper-forms the scenario when only 8 GPRs and 8 XMM registers are used. However, our results also show that using 12 GPRs mid 12 XMM registers can achieve as competitive performance as employing 16 GPRs and 16 XMM registers. © Springer- Verlag Berlin Heidelberg 2006.