Power effective design of 10T D-FF using MTCMOS technique

Abstract

In digital environment, circuit design is an important parameter to take under consideration for making a compact and power efficient design. A high speed low power compact design is a challenge to all digital circuit and from these parameters power consumption with high speed is always desirable. The main important point of this paper is to provide, power effective model of 10T D-FF using MTCMOS technique, as a new low power solution for VLSI design. MTCMOS (multi threshold CMOS) is more effective circuit level technique that gives a high performance and low power design by utility of both low and high threshold voltage transistor. After implementing MTCMOS technique in our desired circuit power consumption reduces from 602.9E-9 to 189.4E-12 in active mode and up to 22.28E-12 in standby mode, and the static leakage power reduces from 7.85E-12 to 4.14E-13 in standby mode. The overall process is carried out on cadence virtuoso tool at 45 nm technology.