Design of comparator in sigma-delta ADC using 45 nm CMOS technology

Abstract

An energy efficient comparator circuit for sigma-delta ADC has been proposed in this paper. The proposed comparator uses CMOS two-stage opamp. The designed opamp shows 89 dB gain, 2.3 GHz UGB, and 65° phase margin with 1.02 mW power dissipation. Both opamp and comparator output responses have been extracted from the circuit at ± 1 V operating voltage. The proposed circuit is simulated in Cadence Analog Design Environment with gpdk045 nm library. The comparator circuit has been designed such that the simulation result ranges between -100 and 500 mV.