Abstract
Two electrical engineering applications from industry partners dealing with sparse matrices were analyzed regarding cache efficiency and scalability on modern multi core systems. Two different contemporary multi-core architectures have been investigated, namely Intel's Westmere and AMD's Magny-Cours. This paper can be regarded as a continuation of the investigations presented in [14] and [15]. In addition, the SuiteSparseQR library for efficiently computing QR factorizations of sparse matrices was evaluated regarding scalability and cache efficiency. © 2011 Springer-Verlag Berlin Heidelberg.
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Müller, T., Trinitis, C., & Smajic, J. (2011). Cache efficiency and scalability on multi-core architectures. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6873 LNCS, pp. 88–97). https://doi.org/10.1007/978-3-642-23178-0_8
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