The simplest and most common approach to computer division is digit recurrence, an iterative process whereby at each step, a multiple of the divisor is subtracted from the current remainder and the quotient is updated accordingly by appending a fixed number of bits k, determined by the underlying radix, r = 2k. Thus, quotient convergence is linear, resulting in fairly high latencies of high-precision operations for the most common radices, r = 2, 4, and 8.
CITATION STYLE
Russinoff, D. M. (2019). SRT Division and Square Root. In Formal Verification of Floating-Point Hardware Design (pp. 183–202). Springer International Publishing. https://doi.org/10.1007/978-3-319-95513-1_10
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