High-performance computing based on high-speed dynamic reconfiguration

Abstract

Currently, demand for implementing all systems including a processor, a peripheral circuit, and a dedicated circuit onto a field programmable gate array (FPGA) is gaining. However, related to the demand, an important issue is that soft-core processors implemented on FPGAs have lower performance than custom processors or FPGA's hard-core processors. Such low performance of soft-core processors on FPGAs is attributable to their look-up table (LUT) and Switching Matrix (SM) architectures. Therefore, under current implementation, such a soft-core processor cannot be used to produce a high-performance system. Instead, a custom processor or an FPGA's hard-core processor must be implemented onto the system along with an FPGA. However, if the FPGA's programmability can be exploited fully, then the performance of soft-core processors and circuits on its programmable gate array can be increased. The key technology is a high-speed dynamic reconfiguration. Therefore, this chapter introduces a new soft-core processor architecture called Mono-Instruction Set Computer (MISC) architecture as high-performance computing based on high-speed dynamic reconfiguration.