A packet-aware non-interleaving scheduling algorithm with multiple classes for input-queued Switch

Abstract

A packet-aware non-interleaving scheduling algorithm that has multiple classes according to the packet lengths is proposed, and the latencies and buffer requirement are investigated in comparison with other algorithms. The non-interleaving scheduling algorithm eliminates the complexity of packet reassembly at the output queue. The simulated results show that the packet-aware non-interleaving scheduling inherently improves the latency of the long packets, while the proposed multi-class scheduling complementarily improves the latency of the short packets. The results show that the non-interleaving algorithm is not only feasible for the practical implementation but may have better performance in the latency, output buffer requirement, and implementation complexity viewpoints, if appropriate scheduling algorithm is used. The simulated results are obtained using self-similar traffic generated based on the measured Internet backbone traffic that reflects the predominance of short packets.