Design of a FPGA-based NURBS interpolator

Abstract

In this paper, a NURBS hardware interpolator based on FPGA is designed to perform the feedrate profile scheduling, de-Boor Cox calculation and second-order Talor expansion to realize real-time interpolation. Look-ahead algorithm including curve-scanning, feedrate adjustment and acceleration/ deceleration planning is implemented in the computer to release the computational load of the interpolator, whereas a motion control card with DSP+FPGA architecture receives the pre-processed results from the look-ahead circuit through PCI bus, and sequently performs the interpolation task in the FPGA and position servo control in the DSP. Experiments are carried out to verify the feasibility of this interpolator. The results imply the FPGA can finish the interpolation within 0.5ms, meanwhile its resource utilization and the calculation speed can compromise to satisfy the practical application. © 2011 Springer-Verlag.