Wideband fully-programmable dual-mode CMOS analogue front-end for electrical impedance spectroscopy

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Abstract

This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm2, is capable of an operational bandwidth of 8 MHz and a linear gain in the range between -6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μA. Each CR channel occupies an area of 0.21 mm2. The chip consumes between 530 μA and 690 μA per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis.

Figures

  • Figure 1. Conceptual arrangement of a dual-mode EIS measurement system with arrays of interdigitated electrodes (IDEs) to measure solution impedance and electrode/interface impedance. The solution impedance can be measured using a tetrapolar configuration by injecting a differential current, IEXT , through an electrode and measuring the differential voltage across a second electrode. Electrode/interface impedance can be measured by exciting an electrode with a voltage source, VEXT , and reading the current flowing through the electrode. In the example in the figure, the same external source is used on multiple electrodes.
  • Figure 2. Example of measured capacitance over time of an IDE test strip shown in the figure inset. The average values of the capacitance are reported in the text for different types of IDEs. For convenience, only the first 150 s of measurement are shown. The values reported in the text refer to the steady state value after 1800 s. Each IDE test strip consists of two equal IDEs with an overall area (W × d) of 3 × 5.5 mm2. Each IDE consists of five digits of a length of 2 mm, a width of 0.3 mm and a spacing of 0.3 mm. The distance between the IDEs is 3 mm.
  • Figure 3. Chip architecture.
  • Figure 4. Architecture of the current-mode channel with automatic gain compensation.
  • Figure 5. Schematic of the Class AB op-amp used to implement the TIA and the programmable gain amplifier (PGA).
  • Figure 6. (a) Schematic of a TIA with the sensor model and noise sources; (b) simulated open-loop gain of the TIA op-amp and noise gain with different values of the compensation capacitor, CC.
  • Figure 7. Transient simulation of the adaptive PD unit at 10 kHz. The relaxation current is set to (a) 10 nA and (b) 100 nA and switched at the same frequency as the input signal with a 25% duty cycle. The output capacitor of the PD (external) is 300 pF.
  • Figure 8. Current-mode amplifier model. (a) Architecture (b) schematic of the input TC with noise sources.

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CITATION STYLE

APA

Valente, V., & Demosthenous, A. (2016). Wideband fully-programmable dual-mode CMOS analogue front-end for electrical impedance spectroscopy. Sensors (Switzerland), 16(8). https://doi.org/10.3390/s16081159

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