Co-modeling methodology for semiconductor manufacturing using DEVS simulation

Abstract

A simulator with flexibility and modularity has been designed and realized by applying DEVS formalism and co-modeling method. DEVS formalism is the mathematical formalism to express simulation based real-time job scheduling system which dynamically uses dispatching rules in different situation with discrete event system. Co-modeling method distinguishes the overall characteristics of systems and detailed characteristics of systems. A simulator to evaluate dispatching rules and a simulator for FAB simulation were separately made. The simulator to evaluate dispatching rules was operated based on logical time and FAB simulator was operated using logical time and real time alternatively so that a framework for the quick and accurate simulation test can be realized. © 2012 Springer-Verlag Berlin Heidelberg.