The ASIC physical design process is a complex optimization problem with various objectives such as minimum chip minimum wire length, area, minimum of vias. The main aims of optimization are to improve the performance and reliability etc., of the ASIC design process. The objectives mentioned can be achieved through the effective implementation of floorplanning before other steps are implemented. In this study, a pseudo code is developed for floorplanning using geometric programming to achieve global optima. This study uses simulations performed using MATLAB GGP toolbox.
CITATION STYLE
Bala Dastagiri, N., Hari Kishore, K., Gunjan, V. K., Janga Reddy, M., & Fahimuddin, S. (2019). Geometric programming-based automation of floorplanning in ASIC physical design. In Lecture Notes in Electrical Engineering (Vol. 500, pp. 463–468). Springer Verlag. https://doi.org/10.1007/978-981-13-0212-1_48
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