A new neural network approach to the floorplanning of hierarchical VLSI designs

Abstract

In this paper, we introduce a new neural network approach to the floorplanning of VLSI (Very Large Scale Integrated circuit) designs. The network used is a Kohonen setf-organising map. An abstract specification of the design is converted to a set of appropriate input vectors fed to the network at random. At the end of the process, the map shows a 2-dimensional plane of the design in which the modules with higher connectivity axe placed adjacent to each other, hence minimizing total connection length in the design. The approach can be extended to consider external connections and is able to floorplan a rectilinear boundary. These features makes the approach capable of floorplanning hierarchically specified designs. Since only the global ordering phase is needed for the floorplanner, the process is fast.