In general on-chip communication protocols, such as OCP[1], can be specified and represented with finite state machines (FSM). Such communication protocols are basically collections of individual transactions or commands, such as simple read/write and bust read/write, and each transaction or command can be specified with a FSM. So a given communication protocol can be represented with a set of FSMs which work jointly. Based on these FSM-based specifications, we have been developing not only pure formal and semi-formal verification techniques using FSMs as specifications, but also synthesis and debugging techniques, such as automatic generation of protocol converters and post-silicon verification/debugging supports. In this paper, we show first how FSM-based specifications can describe sate-of-the-art on-chip communication protocols, and then their application to such synthesis and verification/debug for SoC designs are presented. © 2011 Springer-Verlag.
CITATION STYLE
Fujita, M. (2011). Synthesizing, verifying, and debugging SoC with FSM-based specification of on-chip communication protocols. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6996 LNCS, pp. 43–50). https://doi.org/10.1007/978-3-642-24372-1_4
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