Coding techniques in Verilog for finite state machine designs in FPGA

Abstract

Coding techniques in Verilog HDL of finite state machines (FSMs) for synthesis in field programmable gate arrays (FPGAs) are researched, and the choice problem the best FSM coding styles in terms of an implementation cost (area) and a performance (speed) are considered. The problem is solved empirically by executing of experimental researches on the FSM benchmarks. Seven coding styles in Verilog are offered for coding of combinational circuits for FSMs from those two best styles are selected. On the basis of these two coding styles of combinational circuits six coding styles of FSMs are offered. The efficiency of the coding styles was researched for the synthesis of FSM benchmarks in two classes of programmable devices: CPLD (Complex Programmable Logic Device) and FPGA. The experimental results showed that the choice of coding styles allows to reduce the implementation cost of FSMs by a factor of 3.06 and to increase the speed of FSMs by a factor of 1.6. In conclusion, the prospective directions for coding styles of FSMs are specified.