AM-Trie: A high-speed parallel packet classification algorithm for network processor

Abstract

Nowadays, many high-speed Internet services and applications require high-speed multidimensional packet classification, but current high-speed classification often use expensive and power-slurping hardware (such as TCAM and FPGA). In this paper, we present a novel algorithm, called AM-Trie (Asymmetrical Multi-bit Trie). Our algorithm creatively use redundant expression to shorten the height of Trie; use compression to reduce the storage cost and eliminate the trace back to enhance the search speed further. Moreover, AM-Trie is a parallel algorithm and very fit for the "multi-thread and multi-core" features of Network Processor; it has good scalability, the increase of policy number influences little to its performance. Finally, a prototype is implemented based on Intel IXP2400 Network Processor. The performance testing result proves that AM-Trie is high-speed and scalable, the throughput of the whole system achieves 2.5 Gbps wire-speed in all situations. © Springer-Verlag Berlin Heidelberg 2006.