Interconnection structures in FPGAs increasingly contribute more to the delay and power consumption. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronics products. However, the benefits of such a technology have not been sufficiently explored yet. This paper introduces a novel 3-D FPGA, where logic, memory and I/O resources are assigned to different layers. Experimental results prove the efficiency of our architecture for a wide range of application domains, since we achieve average performance improvement and power saving of 30% and 10%, respectively. © 2011 Springer-Verlag.
CITATION STYLE
Sidiropoulos, H., Siozios, K., & Soudris, D. (2011). A framework for architecture-level exploration of 3-D FPGA platforms. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6951 LNCS, pp. 298–307). https://doi.org/10.1007/978-3-642-24154-3_30
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