Transient Characterization of interface traps in 4H-SiC MOSFETs

Abstract

High density of interface traps at the SiC-SiO2 interface gives rise to lower mobilities and currents in SiC MOSFETs. Detailed investigations are performed to measure and characterize these interface traps using experimental and modeling methods [1-3]. Recent measurements of threshold voltage instabilities by fast I-V methods have shown that the SiC-SiO 2 interface not only contains fast interface traps, but also slower near-interface and oxide traps [4,5]. Steady state modeling and simulations cannot characterize the effects of each of these defects. We have hence developed a detailed time dependent modeling scheme for dynamic interface trap occupation, and incorporated it into our 2D transient device simulator. We use the transient modeling to separate out and individually characterize interface, near-interface and oxide traps in 4H-SiC MOS devices.