ULPD and CPTL pull-up stages for differential cascode voltage switch logic

Abstract

Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation.