Modeling and simulation of efficient march algorithm for memory testing

Abstract

Semiconductor memories are considered one of the most important aspects of modern microelectronics. Memories are the most important universal components in SoC (System on Chip) today. Almost all SoC's contain some type of embedded memories, such as ROM, RAM, DRAM and flash memory. Testing them becomes a challenge as these devices become more complex. The modeling and simulation of Memory BIST is presented in this paper. The architecture is implemented using Hardware Description Language and an area overhead is analyzed. The LR algorithm is implemented on to test the SRAM faults like stuck at faults, inversion coupling faults, linked faults etc. © 2010 Springer-Verlag Berlin Heidelberg.